臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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	Repositories
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	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

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Institution	Date	Title	Author
中原大學	2010-12	Obstacle-Avoiding Electromigration Aware Wire Planning for Analog Circuits	Cheng-Chiang Lin;Hsin-Hsiung Huang; Hsi-An Chien;Tsai-Ming Hsieh
中原大學	2010-05	Technology Remapping for Engineering Change with Wirelength Considertion	Yao-Kai Yeh; Jui-Hung Hung; Yung-Sheng Tseng; Tsai-Ming Hsieh
中原大學	2010-04	Optimal Supply Voltage Assignment underTiming, Power and Area Constraints	Hsi-An Chien;Cheng-Chiang Lin;Hsin-Hsiung Huang; Tsai-Ming Hsieh
中原大學	2009-12	ILP-Based Optimal Multi-Threshold Voltages Assignment under Performance Constraints	Chun-Hua Chung; Hsin-Hsiung Huang; Hsi-An Chien ; Tsai-Ming Hsieh
中原大學	2009-11	Graph-based Wire Planning for Analog Circuits	Cheng-Chiang Lin; Pei-Shan Wu;Jiun-Ying Yu;Yu-Cheng Lin; Hsin-Hsiung Huang; Tsai-Ming Hsieh
中原大學	2009-11	The Implementation of a Line Following Maze Robot for Mobile Robot System Courses	Hsin-Hsiung Huang;Chyi-Shyong Lee;Juing-Huei Su;Chia-Lung Yang;Tsai-Ming Hsieh
中原大學	2009-08	EngineeringChange Order-Driven Routing Tree Construction	Cheng-Chiang Lin; Hsin-Hsiung Huang; Yu-Cheng Lin;Tsai-Ming Hsieh
中原大學	2009-08	Technology Remapping for Engineering Change with Wirelength Consideration	Yung-Sheng Tseng;Yao-Kai Yeh;Mely Chen Chi;Tsai-Ming Hsieh
中原大學	2009-06	Timing-Driven X-Architecture Routing Tree Constructio Among Rectangular and Non-rectangular Obstacles	Shu-Ping Chang; Hsin-Hsiung Huang; Cheng-Chiang Lin; Tsai-Ming Hsieh
中原大學	2009-05	Timing-Driven Non-Rectangular Obstacles-Avoiding Routing Algorithm for the X-Architecture	Hsin-Hsiung Huang;Shu-Ping Chang;Yu-Cheng Lin; Tsai-Ming Hsieh

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